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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual J-K Flip-Flop with Set and Reset
High-Performance Silicon-Gate CMOS
The MC74HC112 is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs. The HC112 is identical in function to the HC76, but has a different pinout. * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Similar in Function to the LS112 Except When Set and Reset are Low Simultaneously * Chip Complexity: 100 FETs or 25 Equivalent Gates
16
MC74HC112
N SUFFIX PLASTIC PACKAGE CASE 648-08
1
16 1
D SUFFIX SOIC PACKAGE CASE 751B-05
16 1
DT SUFFIX TSSOP PACKAGE CASE 948F-01
ORDERING INFORMATION MC74HCXXXN MC74HCXXXD MC74HCXXXDT Plastic SOIC TSSOP
LOGIC DIAGRAM
PIN ASSIGNMENT
CLOCK 1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RESET 1 RESET 2 CLOCK 2 K2 J2 SET 2 Q2
SET 1 K1 CLOCK 1 J1 RESET 1
4 2 1 3 15 6 Q1 5 Q1
K1 J1 SET 1 Q1 Q1 Q2 GND
SET 2 K2 CLOCK 2 J2 RESET 2
10 12 13 11 14 PIN 16 = VCC PIN 8 = GND 7 Q2 9 Q2
FUNCTION TABLE
Inputs Set L H L H H H H H H H Reset Clock H L L H H H H H H H X X X J X X X L L H H X X X K X X X L H L H X X X Outputs Q Q H L L H L* L* No Change L H H L Toggle No Change No Change No Change
L H
* Both outputs will remain low as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously.
10/95
(c) Motorola, Inc. 1995
1
REV 6
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* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). Vin = VCC or GND 6.0 4 40 80 A Iout = 0 A NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
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MAXIMUM RATINGS*
MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
RECOMMENDED OPERATING CONDITIONS
MC74HC112
Symbol
Vin, Vout
Symbol
Symbol
VCC
Vout
Tstg
ICC
Iout
VCC
Vin
PD
TL
VOH
tr, tf
Iin
VOL
ICC
TA
VIH
VIL
Iin
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP)
Storage Temperature
Power Dissipation in Still Air
DC Supply Current, VCC and GND Pins
DC Output Current, per Pin
DC Input Current, per Pin
DC Output Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Input Rise and Fall Time (Figure 1)
Operating Temperature, All Package Types
DC Input Voltage, Output Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Maximum Quiescent Supply Current (per Package)
Maximum Input Leakage Current
Maximum Low-Level Output Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Parameter
Parameter
Parameter
Plastic DIP SOIC Package TSSOP Package
Vin = VIH or VIL |Iout| 20 A
Vin = VIH or VIL |Iout| 20 A
Vin = VCC or GND
Vin = VIH or VIL |Iout| |Iout|
Vin = VIH or VIL |Iout| |Iout|
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
v
v
v
v
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
Test Conditions
- 0.5 to VCC + 0.5
- 1.5 to VCC + 1.5
- 65 to + 150
- 0.5 to + 7.0
2 - 55 Min 2.0 Value
v 4.0 mA v 5.2 mA
v 4.0 mA v 5.2 mA
0 0 0
0
50
25
20
260
750 500 450
+ 125
1000 500 400
VCC
Max
6.0
VCC V
6.0
4.5 6.0
2.0 4.5 6.0
4.5 6.0
2.0 4.5 6.0
2.0 4.5 6.0
2.0 4.5 6.0
Unit
Unit
mW
mA
mA
mA
_C
_C
_C
ns
V
V
V
V
V
- 55 to 25_C
0.1
1.5 3.15 4.2
0.26 0.26
3.98 5.48
0.1 0.1 0.1
1.9 4.4 5.9
0.3 0.9 1.2
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Guaranteed Limit
v 85_C v 125_C
High-Speed CMOS Logic Data DL129 -- Rev 6 1.0 1.5 3.15 4.2 0.33 0.33 3.84 5.34 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2
v
1.0 1.5 3.15 4.2 0.40 0.40 3.70 5.20 0.1 0.1 0.1 1.9 4.4 5.9 0.3 0.9 1.2
v
Unit
A V V V V
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NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). * Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
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AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol tPLH, tPHL tPLH, tPHL tPLH, tPHL tTLH, tTHL fmax Cin Maximum Input Capacitance Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Propagation Delay, Set to Q or Q (Figures 2 and 4) Maximum Propagation Delay, Reset to Q or Q (Figures 2 and 4) Maximum Propagation Delay, Clock to Q or Q (Figures 1 and 4) Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) Parameter VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- - 55 to 25_C 165 33 28 155 31 26 125 25 21 6.0 30 35 10 75 15 13 Guaranteed Limit
High-Speed CMOS Logic Data DL129 -- Rev 6
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Symbol
CPD
trec
tr, tf
tsu
tw
tw
th
Power Dissipation Capacitance (Per Flip-Flop)*
Maximum Input Rise and Fall Times (Figure 1)
Minimum Pulse Width, Set or Reset (Figure 2)
Minimum Pulse Width, Clock (Figure 1)
Minimum Recovery Time, Set or Reset Inactive to Clock (Figure 2)
Minimum Hold Time, Clock to J or K (Figure 3)
Minimum Setup Time, J or K to Clock (Figure 3)
Parameter
3 VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 20 4.5 6.0 - 55 to 25_C Typical @ 25C, VCC = 5.0 V 1000 500 400 100 20 17 100 20 17 80 16 14 80 16 14 3 3 3 Guaranteed Limit 1000 500 400 100 20 17 100 20 17 125 25 21 125 25 21 205 41 35 195 39 33 155 31 26 4.8 24 28 10 95 19 16 35 3 3 3 1000 500 400 120 24 20 120 24 20 150 30 26 150 30 26 250 50 43 235 47 40 190 38 32 110 22 19 4.0 20 24 10 3 3 3
v 85_C v 125_C
v 85_C v 125_C
MC74HC112
MOTOROLA MHz Unit Unit pF pF ns ns ns ns ns ns ns ns ns ns
MC74HC112
SWITCHING WAVEFORMS
tf 90% 50% 10% tw 1/fmax tPLH tPHL Q or Q 90% 50% 10% Q OR Q tTLH tTHL CLOCK Q OR Q tr tw VCC SET OR RESET 50% GND tPHL 50% tPLH 50% trec VCC 50% GND
VCC GND
CLOCK
Figure 1.
Figure 2.
VALID VCC J OR K 50% GND tsu CLOCK th VCC 50% GND DEVICE UNDER TEST OUTPUT TEST POINT
CL*
Figure 3.
* Includes all probe and jig capacitance
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
RESET 15, 14 5, 9 CL J 3, 11 CL
Q
K
2,12 CL CL
CL CL
CL
CL CL
CL
CL
CLOCK
1, 13 CL 6, 7 Q
SET
4, 10
CL
CL
MOTOROLA
4
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC112
OUTLINE DIMENSIONS
N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R
B
1 8
-A -
16 9
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0 0 10 10 0.020 0.040 0.51 1.01
F S
C
L
-T - H G D 16 PL 0.25 (0.010)
M
SEATING PLANE
K
J TA
M
M
-A -
16 9
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-B -
1 8
P 8 PL 0.25 (0.010)
M
B
M
G F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019
K C -T SEATING -
PLANE
R X 45
M D 16 PL 0.25 (0.010)
M
J
T
B
S
A
S
High-Speed CMOS Logic Data DL129 -- Rev 6
5
MOTOROLA
MC74HC112
OUTLINE DIMENSIONS
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K
K1
2X
L/2
16
9
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N J
N 0.25 (0.010) 0.15 (0.006) T U
S
A -V- N F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
M
DIM A B C D F G H J J1 K K1 L M
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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*MC74HC112/D*
MC74HC112/D High-Speed CMOS Logic Data DL129 -- Rev 6

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